library ieee;
use ieee.std_logic_1164.all;

entity FA is
  port(
    A: in std_logic;
    B: in std_logic;
    Cin: in std_logic;
    S: out std_logic;
    Cout: out std_logic
  );
end FA;

architecture rtl of FA is
  begin
    S <= A xor B xor Cin;
    Cout <= (A and B) or (B and Cin) or (A and Cin);
end architecture rtl;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity RCA is
port(
  A   : in std_logic_vector(31 downto 0);
  B   : in std_logic_vector(31 downto 0);
  Cin : in std_logic;
  Sum : out std_logic_vector(31 downto 0);
  CO  : out std_logic;
  V   : out std_logic
);
end RCA;

architecture rtl of RCA is
  signal c: std_logic_vector (32 downto 0);
  begin
    c(0) <= Cin;
    rippleAdd: for i in 0 to 31 generate
      cellFA: entity work.FA port map (A=> A(i), B=>B(i), Cin=>c(i), S=>Sum(i), Cout=>c(i+1));
    end generate rippleAdd;
    CO <= c(32);
    V <= c(32) xor c(31);
end architecture rtl;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity SLTU is
port(
  CO  	 : in std_logic;
  Cout   : out std_logic_vector(31 downto 0)
  
);
end SLTU;

architecture rtl of SLTU is
  begin
    Cout <= (31 downto 1 => '0') & (CO);
end architecture rtl;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity SLT is
port(
  MSB  	 : in std_logic;
  V  	 : in std_logic;
  Cout   : out std_logic_vector(31 downto 0)
);
end SLT;

architecture rtl of SLT is
  begin
    Cout <= (31 downto 1 => '0') & (((not MSB) AND(not V))or(MSB AND V) );
end architecture rtl;
---------------------------------------------------------------------------------